This is a senior technical leadership opportunity focused on driving complex SoC physical implementation from RTL handoff through final GDSII delivery.
You will own physical design strategy, methodology, schedules, quality checkpoints, and execution across advanced technology nodes.
The role spans floorplanning, place and route, clocking, timing closure, power optimization, and physical verification.
You will work closely with Architecture, RTL Design, Verification, DFT, Power, Packaging, and Signal Integrity teams to deliver high-performance silicon.
Beyond hands-on technical ownership, you will mentor physical designers and establish scalable design practices and quality standards.
The position offers the opportunity to influence cutting-edge semiconductor products where performance, power efficiency, and security are critical.
The organization supports flexible work arrangements and is open to candidates across the United States.
Accountabilities
- Lead end-to-end ASIC physical design activities from RTL handoff, floorplanning, and place-and-route through final GDSII delivery.
- Define physical implementation strategies, execution schedules, methodologies, design checkpoints, and quality standards for complex SoC programs.
- Develop and execute floorplans for large, hierarchical SoCs, including IP and macro placement, physical partitioning, power grid architecture, clock distribution, die dimensions, and physical constraints.
- Lead block-level and top-level place-and-route using industry-standard Cadence and/or Synopsys EDA toolchains.
- Drive timing closure and convergence across multiple corners, modes, voltage domains, and operating conditions while optimizing power, performance, and area.
- Lead CTS implementation and optimize clock skew, latency, and clock power.
- Own physical integrity and sign-off activities, including IR/EM analysis, thermal considerations, DRC, LVS, ERC, and other physical verification requirements.
- Implement and validate low-power design methodologies, including UPF/CPF flows.
- Partner with DFT and physical design teams to ensure scan insertion, BIST structures, test modes, timing, and physical implementation are robust.
- Collaborate with Packaging and SI teams on bump planning, floorplan constraints, package-aware timing, and related integration requirements.
- Translate product and architectural requirements into physical design objectives, budgets, constraints, schedules, and measurable deliverables.
- Conduct design reviews, maintain high standards for physical design quality, and ensure reliable execution through tapeout.
- Provide technical leadership, mentorship, coaching, and guidance to junior and mid-level physical designers.
- Champion continuous improvement across physical design flows, automation scripts, methodologies, and engineering best practices.
- Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; an advanced degree is preferred.
- 8+ years of hands-on experience in ASIC Physical Design with a strong record of multiple successful tapeouts.
- Experience implementing advanced-node designs, preferably across technology nodes ranging from 16nm to 3nm.
- Deep expertise in floorplanning, place and route, clock-tree synthesis, static timing analysis, timing closure, physical verification, sign-off, and low-power design.
- Strong hands-on proficiency with Cadence and/or Synopsys physical design toolchains.
- Solid understanding of RTL-to-GDS flows, SoC integration, design architecture trade-offs, and physical implementation challenges.
- Experience with UPF and/or CPF methodologies for low-power design.
- Strong understanding of PPA optimization, congestion mitigation, power integrity, timing, and physical design constraints.
- Ability to translate product requirements into physical design goals, budgets, constraints, execution plans, and deliverables.
- Strong analytical, debugging, and problem-solving abilities with exceptional attention to detail.
- Excellent communication skills, with the ability to explain technical decisions and collaborate effectively across architecture, RTL, verification, DFT, power, packaging, and other engineering teams.
- Demonstrated ability to provide technical leadership and mentor engineers while maintaining ownership of schedules, quality, and delivery.
- Comfortable working proactively in a distributed and fast-moving engineering environment.
- Competitive salary.
- Equity participation through Incentive Stock Options (ISO).
- Employer-paid medical insurance plan.
- Health Savings Account (HSA) with employer contributions.
- Dental and vision reimbursement account.
- 401(k) retirement plan with employer matching.
- Flexible work location with remote options across the United States.
- Flexible time off.
- Opportunity to work on advanced semiconductor and SoC technologies with significant performance, power, and security requirements.
- Opportunity to provide technical leadership and shape physical design methodologies and engineering practices.
We use an AI-powered matching process to ensure your application is reviewed quickly, objectively, and fairly against the role's core requirements. Our system identifies the top-fitting candidates, and this shortlist is then shared directly with the hiring company. The final decision and next steps (interviews, assessments) are managed by their internal team.
We appreciate your interest and wish you the best!
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